ATMEGA169P-16MCHR【PDF 274/274 页】MCU AVR 16KB FLASH 16MHZ 64-VQFN

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录3753

270页 271页 272页 273页 [274页]

8018P–AVR–08/10

ATmega169P

feature is similar to the OC0A toggle in CTC mode, except the double buffer feature of the Out-

put Compare unit is enabled in the fast PWM mode.

14.7.4

Phase Correct PWM Mode

The phase correct PWM mode (WGM01:0 = 1) provides a high resolution phase correct PWM

waveform generation option. The phase correct PWM mode is based on a dual-slope operation.

The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOTTOM. In non-

inverting Compare Output mode, the Output Compare (OC0A) is cleared on the compare match

between TCNT0 and OCR0A while upcounting, and set on the compare match while down-

counting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation

has lower maximum operation frequency than single slope operation. However, due to the sym-

metric feature of the dual-slope PWM modes, these modes are preferred for motor control

applications.

The PWM resolution for the phase correct PWM mode is fixed to eight bits. In phase correct

PWM mode the counter is incremented until the counter value matches MAX. When the counter

reaches MAX, it changes the count direction. The TCNT0 value will be equal to MAX for one

timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 14-7.

The TCNT0 value is in the timing diagram shown as a histogram for illustrating the dual-slope

operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal

line marks on the TCNT0 slopes represent compare matches between OCR0A and TCNT0.

Figure 14-7. Phase Correct PWM Mode, Timing Diagram

The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The

Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM

value.

In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the

OC0A pin. Setting the COM0A1:0 bits to two will produce a non-inverted PWM. An inverted

PWM output can be generated by setting the COM0A1:0 to three (See Table 14-5 on page 103).

The actual OC0A value will only be visible on the port pin if the data direction for the port pin is

TOVn Interrupt Flag Set

OCnx Interrupt Flag Set

TCNTn

Period

OCn

(COMnx1:0 = 2)

(COMnx1:0 = 3)

OCRnx Update

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式